The present invention relates to apparatus and methods of packaging and testing die for use in, for example, chip scale packages and other similar devices.
Conventional packaging of die in microelectronic devices involves two levels of packaging. FIG. 1 shows a first level of packaging of a die package 40 in accordance with the prior art. In this example, a die (or integrated circuit) 20 is attached to a lead frame 22 having a plurality of conductive leads 24 formed thereon. The die 20 is typically attached with a layer of adhesive epoxy or glue. Bonding pads 26 on the die 20 are connected by bonding wires 28 to respective contact pads 30 on the lead frame 22, a technique commonly known as wire-bonding. The contact pads 30 are electrically coupled to an inner end of each conductive lead 24. In this representative example, each conductive lead 24 has an outer end that terminates in a connecting pin 32. The die 20 and lead frame 22 are then encapsulated by a cover 34, thus constituting the first level of packaging. In a second level of packaging, the encapsulated die and lead frame may be mounted to an electronics device, such as by inserting the connecting pins 32 into associated sockets on a printed circuit board and securing the pins in place using solder reflow techniques.
Recently, die have been mounted directly to a substrate, such as a printed circuit board, thus eliminating the lead frame and the first level of packaging. Mounting of the die 20 directly to a circuit board is generally referred to as chip-on-board (COB) packaging. For example, FIG. 2 shows the die 20 mounted directly to a circuit board 40 in a COB or xe2x80x9cflip chipxe2x80x9d packaging arrangement. In this arrangement, the bonding pads 26 are located on a bottom surface of the die 20. The circuit board 40 has a set of terminals or conductive bumps 42 on one surface. As shown in FIG. 2, the die 20 is mounted with the bonding pads 26 of the die 20 facing the surface of the printed circuit board 40 to which the die 20 is being mounted such that the bonding pads 26 make direct contact with the terminals 42. Thus, the bonding wires 28 and lead frame 22 are eliminated.
It is customary to provide a layer of material known as a glob top or encapsulating layer 44 over the die 20 to hermetically seal the die 20. The glob top 44 serves as a chemical insulator protecting the die 20 from humidity, oxidation, and other harmful elements. The glob top 44 also protects the die 20 mechanically and relieves mechanical stress in the die 20.
It is also known to stack die on top of another die to save space on the printed circuit board. For example, FIG. 3 shows a packaging arrangement having an inner die 50 mounted in a flip chip arrangement on the circuit board 40 such that the bonding pads 26 of the inner die 50 are in direct contact with the conductive terminals 42 on the circuit board 40. An outer die 52 is attached to the inner die 50. Bonding wires 28 extend from a set of second bonding pads 54 on the outer die 52 to a set of second terminals 56 on the circuit board 40. A glob top 44 is then applied over the stacked die to hermetically seal and protect the die 50, 52.
A conventional method of testing the stacked die 50, 52 arrangement is to test the package after it has been completely assembled. Testing of the die prior to packaging is typically limited to spot-checking of a random sample of the die while the die are attached to the wafer. FIG. 4 shows a conventional method 60 of assembling and testing stacked die on a printed circuit board (PCB). In a first step 62, the inner die 50 is attached to the PCB 40 with the contact pads 26 of the inner die 50 in contact with the terminals 42. The outer die 52 is then attached to the inner die 50 in a second step 64, and the glob top is applied to encapsulate the die in a third xe2x80x9csealingxe2x80x9d step 65.
In a fourth xe2x80x9ctestingxe2x80x9d step 66, input signals are systematically applied to the package to test all or some aspects of component performance, including speed, functionality, open circuits, shorts, and bum-in testing. In a fifth xe2x80x9cdeterminationxe2x80x9d step 68, it is determined whether the package has performed the tests successfully. If so, the assembly and test method is complete 70.
If the package has not performed the tests successfully, it is determined whether the package has previously been reworked 72. If the package has been previously reworked but continues to fail the tests, the entire package is discarded in a xe2x80x9crejectionxe2x80x9d step 74, including the inner die, the outer die, and in some cases even the PCB. If the package has not been previously reworked, however, the package is reworked 76, and the package is returned to the testing step 66 for evaluation.
Although successful results have been achieved using the above-referenced die packages, and methods of assembling and testing such die packages, certain disadvantages have been encountered. For example, because the glob top 44 is designed to protect the die from environmental and mechanical stress, the materials used for the glob top are typically poor thermal conductors. Due to relatively poor heat dissipation through the glob top, the die or the PCB may become hotter than desirable, particularly for stacked die or high-power die applications.
Furthermore, because the conventional method of testing the die package involves testing after the inner die has been attached to the PCB and the outer die has been attached to the inner die, if a package does not pass a test successfully, the stacked die and PCB package must undergo a time-consuming and costly rework procedure, or must be discarded entirely. This is particularly true if the testing is performed after the glob top has been applied.
The present invention is directed to apparatus and methods of packaging and testing die for use in, for example, chip scale packages and other similar devices. In one aspect of the invention, a stacked die package comprises a packaging substrate including a first surface having a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and having a plurality of first bond pads, and a second die attached to the first die and having a plurality of second bond pads, the first and second bond pads being electrically coupled to at least some of the conductive leads. When the stacked die package is engaged with, for example, a circuit board, the first surface of the packaging substrate is proximate the circuit board so that the packaging substrate at least partially encloses and protects the first and second die. The properties and dimensions of the packaging substrate are tailored to optimize the operational environment of the die, including improving thermal dissipation and enhancing performance of the die. In an alternate aspect, the packaging substrate comprises an electrically-conductive substrate and an electrically insulative layer is formed between the conductive leads and the packaging substrate.
In another aspect of the invention, the first bond pads are electrically coupled to the conductive leads by wire-bonding. Alternately, the first bond pads are in direct contact with the conductive leads in a flip chip arrangement. In another aspect, the first and second die are sealed within an encapsulating layer for protection.
A method of packaging and testing a die package in accordance with the invention includes testing a die having a plurality of bond pads formed thereon, determining that the die has tested successfully, providing a packaging substrate including a first surface having a recess formed therein and a plurality of conductive leads formed thereon, attaching the die to the packaging substrate within the recess and with the bond pads electrically coupled to at least some of the conductive leads to form the die package, and testing the die package. By integrating the testing and packaging of the die package, overall efficiency and yield is improved.
In another aspect of the invention, a method of packaging and testing includes determining that the die package has not previously been reworked. Alternately, a method includes reworking the die package. In another alternate aspect, a method includes determining that the die package is salvageable. If so, the die package may be salvaged. Alternately, a method includes sealing the die in an encapsulating layer.
An embodiment of a method of packaging and testing a stacked die package in accordance with the invention includes testing a first die having a plurality of first bond pads formed thereon, determining that the first die has tested successfully, testing a second die having a plurality of second bond pads formed thereon, determining that the second die has tested successfully, attaching the second die to the first die, providing a packaging substrate including a first surface having a recess formed therein and a plurality of conductive leads formed thereon, attaching the first die to the packaging substrate within the recess and with the first and second bond pads electrically coupled to at least some of the conductive leads to form the stacked die package, and testing the stacked die package.